Review of a paper

Title:

“The Case for the Reduced Instruction Set Computer”

Authors:

David A. Petterson

Computer Science Division

University of California

Berkeley, California 94720

and

David R. Ditzel

Bell Laboratiories

Computer Science Research Center

Murray Hill, New Jersey 07974

Summary

The primary objective of this paper is to highlight a novel design approach for computer architecture. This innovative design approach is called Reduced Instruction Set Computer (RISC). Authors have claimed the efficiency of this model over currently running super dominating model called Complex Instruction Set Computer (CISC) by illustrating various design factors that favors the RISC model.

One of the design factors for computer architecture cost-effectiveness. Comparing the cost for implementing RISC, CISC requires more cost for hardware manufacturing as well as more cost on programming and architecture related cost incurred in debugging. Moreover, Complexity of the Architecture increases the overall cost of the system. There are systems like VAX11 or IBM System/38 to justify this statement. So, since CISC model is a complex architecture, it is less cost-effective than RISC model.

Authors have pointed out following reasons for increased complexity which ultimately raises implementation cost.

1. Speed of Memory Vs CPU: Since the core memory slower than CPU in speed, the instructions are implemented in hardware level for better performance. This increases the complexity of the architecture.
2. MicroCode and LSI Technogy: Initially instruction sets were “Hard Wired”, but as the instruction sets grew more complex because of addition of more instruction sets, hard wired was expensive and difficult. So microcode were used to implement this. Now, since more complex instructions can be easily added to microprogram with less hardware cost, complexity is increasing more.
3. Code Density: Code Density is also one of the reasons for the complex architecture. Since memory is used to be expensive, programs are made more compact as a result instruction sets become more complex.
4. Market Strategy: Complex architecture makes size of the system bigger and the market wants bigger system as they think bigger are better. So, this misconception has indirectly favored for the increasing complexity.
5. Upward Compatibility: To support upward compatibility, more functionality is added alone with old functionality, which obviously increases complexity.
6. Support for High Level Languages: To support more and more high level language more instructions are added for handling high level construct.
7. And finally use of multiprogramming techniques are making system more complex.

Then, the paper illustrates how these all complexities are associated with CISC architecture. The paper shows the fact, giving various examples, how the current compliers are not able to use most of the instructions implements expensively in CISC architecture. Authors also claimed that due to rapid changes in technology CISC implementation is becoming more difficult, impracticable and irrational as Design time and Design error rates in CISC implementation are higher.

The next important section of the paper is showing RISC model more favorable to VLSI implementation. By using RISC architecture, the VLSI implementation becomes more feasible, less design time and provides better use of chip area. With all these benefits, RISC potentially gains in speed with simpler design and hence proofs to be cost-effective.

Another factor for the superiority of RISC model is its support for the High-level Language. Using RISC, designing a complier has never been so simple and uniform.

Then the paper reveals the various research projects related to RISC architecture taking place at Berkeley, Bell Labs and IBM.

Finally, authors concluded by claiming RISC as a cost-effective implementation and leaving various questions to the architects that need to be though before designing any new instruction set.

Positive aspects of the paper:

Authors are able to show importance of RISC system in coming future. This paper shows various reasons in detail that increases the system complexity and able to justify how CISC architecture increases the complexity of the whole system. The paper seems pretty success in showing drawbacks of CISC model implementation. The paper also has the good reasons why the VLSI technology is more favorable to RISC architecture. One of the positive aspects of the paper is also the clear explanation on RISC support for the High-level languages in compiler design. The last good aspect but not the least is the conclusive statements that the authors have made which includes number of thinkable questionnaires for the computer architects.

Major Comments:

• The first major disagreement that I have is with its title itself. I believe the contents of the paper is unjustifiable with the title it is given. The paper seems very busy criticizing cases of CISC rather then dissecting own (RISC) cases.

• This paper seems to me only as RISC supportive Philosophy. The paper includes no technical details/proofs that can verify RISC superiority over CISC.

• The most important feature of RISC is pipelining. Unfortunately, there is no single word about pipelining neither word “pipelining” itself.

• There are many instances where writers have tried to justify reasons for CISC being complex. For instances, with the points: Microcode and LSI Technology, Marketing strategy, code density and upward compatibility. Writers have forgotten to mention that with the same reasons, RISC can also be complex.

• The paper has mentioned various data/facts about the existing system about their performance with CISC, but has not verified these facts with any references in most of the cases.

• 
  I am also unable to agree with authors comments on performance/speed. The following equation is commonly using for expressing computer’s performance ability:

Here, The CISC approach attempts to minimize the number of instruction per program, sacrificing the number of cycles per instruction but RISC attempts to reduce the cycles per instruction, sacrificing the number of instructions per program. So without proving which approach is efficient, just the words are not enough.

• Paper lacks good aspects of CISC and drawbacks of RISC, without these, paper cannot be considered fair.

• Authors are not able to verify their own point that how the cost effectiveness increases by decreasing the number of instruction set complexity.

Minor Comments:

• This paper lacks proper standards set for writing technical paper.

• RISC model is not well known approach until now. Explaining about RISC features without giving its clear definition is not effective. Lacking brief introduction of CISC is another drawback.

• The partitioning of body of the paper into various subheadings is also not convincing.

Recommendation:

After reviewing this paper thoroughly and carefully, I would like to recommend not publishing this paper as it is. I have no doubt that this paper carries the sparking approach for computer architecture design which will give new way of thinking for computer architects. I highly recommend for bringing this idea into public as soon as possible, but without making improvements in this paper on the major comments that I had made above, this will only creates confusion and contradiction. After all, this paper is not sufficient enough for challenging CISC architecture that has been dominating since decade. So, to realize RISC is future, I insist a correction of the paper is necessary before it can be published.